VLSI Design Engineer (DFT-STA-Timing-Physical Design)
We are looking for exceptional design engineers to work on complex digital IC projects. The engineer will work in a team-oriented environment to understand and develop specs, write RTL, improve existing verification plans, simulate and debug RTL. The right candidate will have the ability to participate in the definition of architecture and translate these into micro-architecture specifications and RTL. This engineer will take complete ownership of blocks and will work closely with the verification engineers in the verification of these blocks.
Responsibilities:
In this role, the candidate will be working and managing closely our Physical Design House and take part in Physical Synthesis, STA using multi-mode, multi-corner (DMSA) analysis with AOCV/SI, what-if analysis, ECO generation to fix timing/drc violations of large SoC
Working with logic design teams to understand and debug timing constraints, timing problems, getting the correct floor plan, and facilitate logic changes to improve timing
Create timing ECO’s
Create, debug and maintain timing constraints, scripts and methodologies for analysis and runs
Perform deep analysis of timing paths to identify key issues
Propose and review DFT architectures that will enable reliable quick and cheap testing of our device in production
Requirements:
This position requires deep knowledge of ASIC design synthesis, DFT and timing closure flows and methodologies.
The ideal candidate will have the following background:
The ideal candidate will have 5-10 years of hands on experience in timing closure and DFT architecture and implementation with Synopsys or Cadence tools inc. fault coverage analysis and improvement
Hands on knowledge of functional and Test Mode Timing closure.
Hands-on experience in Timing Closure using Synopsys tools (DCT/G, PT-SI) is a must
Hands on experience with timing closure using PrimeTime-SI for large high speed designs and Multi-Mode/Scenario Timing Closure
Deep working knowledge of timing corners/modes, process variations (AOCV) and signal integrity (glitch noise and delta delay noise) for 28nm process node and below as well the ability to perform analysis and fixes
Hands on experience in timing/SDC constraint design from scratch
Hands on experience with tcl scripting for analysis of synthesis, dft and PTSI results and for implementing timing ECOs
Working knowledge of the place and route flow using ICC/ICC2
Low power design methodology is a plus
Experience in ICC for timing closure is a plus